Create a counter that continuously counts odd numbers backwards(i.e from ‘F’ to ‘0’) and display it on 7-sd by using the Verilogcode.
On this part, you are required to use the clock from the FPGAboard. However, the clock frequency is 100 MHz, and it is too fastto be used (10 ?s). Thus, we need to derive a slower clock with aspeed of almost 1 s, which the frequency of it is 1 Hz. Thisprocess is called clock division.
MY FPGA is BASYS 3 and program must be written in verilog. Couldyou please help me? At least write the design code.
If you help me, I will be the happiest person in theworld.
