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  3. 4. bit sequence recognizer [30] submission file f

4. Bit sequence recognizer [30] Submission file for this part: 4.circ Main circuit name: sequencecheck Input pin(s): inputx...

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Electrical Engineering

4. Bit sequence recognizer [30]

  • Submission file for this part: 4.circ
  • Main circuit name: sequencecheck
  • Input pin(s): inputx [1], sysclock [1]
  • Output pin(s): outputr [1]

Derive a minimal state table for a Mealy model FSM that acts asa sequence checker. During four consecutive clock cycles, asequence of four values of the signal x is applied,forming a binary number. The oldest value of x wouldbecome the most significant bit in that binary number. The mostrecent value of x would become the least significantbit.

The FSM will output outputr = 1 when it detects thatthe previous 4 bit sequence was either 0100 or 1010. At all othertimes, including when the previous sequence was not those describedpreviously, outputr = 0. Implement the FSM as a circuit inLogisim Evolution.

Note that much like the last problem, this is not a slidingwindow. After the fourth clock pulse, the circuit resets itself andis ready to take in the next 4 bit sequence.

You will lose a significant portion of credit if your FSM is notminimized.

You will lose a significant portion of credit if yourcombinational logic is not minimized. If you violate both this andthe previous constraint, you will get a 0

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