////VERILOG HDL FOR THE T-flipflop with asynchronous reset
active high input//////////////
module T_ff(T,RST,CLK,Q,Q_bar);
input RST,T,CLK;
output Q,Q_bar;
reg Q,Q_bar;Â Â //consider two variable signals
initial       //assign a reset
state to the flipflop initially(its
not                  Â
mandatory)
   begin
     Q<=1'b0;
     Q_bar<=1'b1;
   end
always@(posedge CLK or posedge RST)//responds when clock raising
edge or RESET raising edge is occurred.
begin
   if(RST==1'b1) begin //Check wheather reset is
pressed or not
        Q<=1'b0;
       Â
Q_bar<=1'b1;
      end
     else begin
       if(T==1'b0) begin //if
T=0 Then assign previous state to the flipflop out put
        Q<=Q;
        Q_bar=Q_bar;
       end
    else begin  //if T=1 then Togle
the state it have prevously
       Q<=~Q;
       Q<=~Q_bar;
     end
    end
  end
endmodule
(if you have any query leave a comment. Thank you)
