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can i ask FSM verilog? ---------------------- module FSM(clk, rst, choice, out); input clk, rst, choice; output reg [1:0]...

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Electrical Engineering

can i ask FSM verilog?

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module FSM(clk, rst, choice, out);

input clk, rst, choice; output reg [1:0] out;

reg [1:0] state, nextstate;
parameter [1:0] S0 = 2’b00, S1 = 2’b01,

S2 = 2’b10, S3 = 2’b11;

always@(posedge clk) begin

if (rst == 1’b0) begin

state <= S0;

end else

end state <= nextstate;

always@(state, rst, choice) begin

case (state) S0 : begin

out = 2’b00;

if (rst == 1’b1) nextstate <= S1; end

S1 : begin
out = 2’b01;
if (choice == 1’b1) nextstate <= S2; else nextstate <=S3;

end

S2 : begin
out = 2’b10;
if (rst == 1’b1) nextstate <= S0;

end

S3 : begin
out = 2’b11;
if (rst == 1’b1) nextstate <= S0;

end endcase

end endmodule

---------------

Q) i knew this kind of fsm verilog code contain sequen, comblogic

how can i rewrite that code with seq + comb+ output logic?

Answer & Explanation Solved by verified expert
3.6 Ratings (393 Votes)
Code your design here module FSMclk rst choice    See Answer
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