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Consider a finite state machine with a control input called mode. When mode = 0, the...

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Electrical Engineering

Consider a finite state machine with a control input calledmode. When mode = 0, the machine operates as a mod-3 down counter,where the outputs are the count values. When mode = 1, themachine's output progresses through the last 4 digits of your WCUID (1133) number (1 digit per clock cycle). Complete each of thesteps which follow.

(a) Draw the state diagram for this machine.
(b) Write RTL Verilog code which implements this design. Submityour printed source code by the due date and time.
(c) Create a test bench to exercise the design through all of itsstates and functions. Submit your test bench source code and asimulation waveform. The simulation waveform must show the digitsof your WCU ID and no one else's.

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4.2 Ratings (668 Votes)
bmodule fsm clock mode Qinput clock    See Answer
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