Create a 4-bit full adder design using VHDL in vivado2017.2.
Project description: You need to create a vhd file for thefour-bit full adder.
Note: Instead of using bit, please use std_logic; instead ofusing bit_vector, please use std_logic_vector.
One simulation source is required, i.e. testbench
Please don't write out on paper. Code written out in text orscreen shots would be very much apprecitated.
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