Design a clocked synchronous state machine with two inputs, Aand B, and a single output Z that is 1 if
(1) A had the “different†value at each of the two previous clockticks, or
(2) B has been 1 since the last time that the first condition wastrue.
Otherwise, the output should be 0.
Design a State assignment using decomposed process. Use Dflip-flops , Design next-state logic using minimal 2-levelNAND-NAND. When designing Next-state logic, don't considermultiple-output minimization.
