Design B: Using behavioral VHDL, design a Mealy-type finitestate machine that detects input test vector that contains thesequence of ‘10’. If the sequence ‘10’ is detected, the output Zshould go high. The input is to be named W, the output is to benamed Z, a Clock input is to be used and an active low reset signal(Resetn) should asynchronously reset the machine.
a) Draw the Mealy-type state diagram for the FSM.
b) Write the VHDL code to implement the FSM.
