find rise time and fall time and logical effort for 5 input NAND
gate
sketch 5 input...
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Electrical Engineering
find rise time and fall time and logical effort for 5 input NANDgate
sketch 5 input NAND gate, then add the capacitors in order to findthe rise time and the falling time ( delays)
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3.8 Ratings (623 Votes)
consider In1 In2 In3 In4 In5to be the inputsof 5input NAND gateThe figure below shows the capacitors in order to find rise andfall timein above fig if In1 In3 In4 In5 1 In2 0 In2 switchesfrom low to high hence nmos transistors except with inputIn1
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