I am trying to write the code for an 8 bit adder in VHDL so thatI can program it onto my Elbert V2 Spartan 3A FPGA DevelopmentBoard, but I keep getting errors. Any ideas what I am doingwrong?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder8bit is
Port ( a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
cin : in STD_LOGIC;
o : out STD_LOGIC_VECTOR(7 downto 0);
cout : out STD_LOGIC);
end adder8bit;
architecture Behavioral of adder8bit is
component fulladder is
Ă‚Â Ă‚Â Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
o : out STD_LOGIC;
cout : out STD_LOGIC
);
end component;
signal c : STD_LOGIC_VECTOR(6 downto 0);
begin
PROCESS (a,b,cin)
BEGIN
o(0) <= a(0) xor b(0) xor cin;
c(0) <= (cin and b(0)) or (cin and a(0)) or (a(0) and b(0));
for i in 1 to 7 loop
o(i) <= a(i) xor b(i) xor c(i-1);
c(i) <= (c(i-1) and b(i)) or (c(i-1) and a(i)) or (a(i) andb(i));
end loop;
cout <= c(6);
END PROCESS;
end Behavioral;
