If you're not answering all three parts of this question, don'tanswer it.
Consider the following FSM VHDL code:
library ieee;
use ieee.numeric_std.all;
entity fsm is
port (clock, input, reset: instd_logic;
output: out std_logic_vector (2downto 0));
end;
architecture bhv of fsmis
type state is (s1, s2, s3,s4);
signal sreg: state;
begin
sreg_machine: process (clock)
begin
if (reset='1')then
sreg <= s1;
output <= \"000\";
elsif(rising_edge(clk)) then
case sregis
when s1=>
output <= \"000\";
if (input='0')then
sreg <= s2;
else
sreg <= s1;
endif;
when s2=>
output <= \"010\";
if (input='1')then
sreg <= s4;
else
sreg <= s3;
endif;
when s3=>
output <= \"100\";
if (input='0')then
sreg <= s1;
else
sreg <= s4;
endif;
when s4=>
output <= \"101\";
if (input='0')then
sreg <= s4;
else
sreg <= s3;
endif;
endcase;
endif;
endprocess;
end architecture;
a) Draw the state diagram for this FSM.
b) What kind of FSM is this? Mealy or Moore? Why?
c) Do you see issues with this FSM VHDL code for simulation orsynthesis? List your answers (if any) and explain how you fix thecoding issue.
