Question B
Write an 8 bit adder module in System Verilog byappropriately connecting two 4 bit adders (the System Verilog codeof a 4 bit adder is available in the lecture notes). Instantiateyour 8 bit adder module on DE2 board. Design a test circuit on DE2board that allows us to test the 8 bit adder using the switches andthe seven segment displays on DE2 board. The test circuit will needthe module you designed for Part (a).
Im Using Quartus II to compile and run the Code , Im using a DE2boards (Cyclone II EP2C35F672 FPGA with 35000 logic elements) .Could you please explain how i can compile and successfully runpart B (above). Im new to using Quartus II
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My Code from Part A
Top Level Code
module hardware_level(SW, HEX0);
input wire [3:0] SW;
output wire [6:0] HEX0;
// create an instance of the project1_7seg module
// project1_7seg (A, B, C, D, S);
project1_7seg inst0( .A(SW[3]), .B(SW[2]), .C(SW[1]), .D(SW[0]),.S(HEX0));
endmodule
7 Segment Display Code
module project1_7seg( A, B, C, D, S);
input wire A, B, C, D;
output wire [6:0]S;
assign S[0] = ~A&~B&~C&D | ~A&B&~C&~D |A&B&~C&D | A&~B&C&D;
assign S[1] = ~A&B&~C&D | A&B&~D |A&C&D | B&C&~D;
assign S[2] = ~A&~B&C&~D | A&B&C;
assign S[3] = B&C&D | ~B&~C&D|~A&B&~C&~D | A&~B&C&~D;
assign S[4] = ~A&D | ~A&B&~C | ~B&~C&D;
assign S[5] = ~A&~B&D | ~A&~B&C | ~A&C&D| A&B&~C&D;
assign S[6] = ~A&~B&~C | ~A&B&C&D |A&B&~C&~D;
endmodule
