Read sections in the TTL data sheets pertaining to the 74LS112ADual J-K flip-flop.
1. For the 74LS112A, what is the maximum clock rate, minimumpulse width for the clock’s high and low levels, worst casepropagation delay of the outputs from the high-to-low clocktransition, and minimum input setup time?
2. Design a nine-step counter to count in the followingsequence. Use J-K flip-flops, NAND gates, and Inverters only.
0011, 0101, 1001, 1000, 1011, 1010, 0110, 0100, 0111, 0011,…
Include in the design a means for resetting the counter to0011.
Provide a circuit diagrams, relevant truth tables, statediagrams and state table.
In addition, provide the excitation functions for the J-Kflip-flops.
