use modelsim write Verilog code for the following digital logiccircuits and then simulate them by writing a testbench module foreach of them ,
(a)The FSMs for the snail problem that is in the slides (a snailcrawls over a tape that has 0 and 1 and smiles if it has detectedthe '10' bits using both Moore and Mealy FSM. Note that the patternis '10' not '01' as in the slides.
(b) A rock-paper-scissor game played by two users (A and B) toindicate who's won or draw then they input their choice. Hint: A'soutput is 1 if A has won, both A's and B's signals is 0 if it was adraw.
