Using behavioral VHDL, design a Mealy-type finite state machine
that detects input test vector that contains...
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Electrical Engineering
Using behavioral VHDL, design a Mealy-type finite state machinethat detects input test vector that contains the sequence of ‘100’.If the sequence ‘100’ is detected, the output Z should go high. Theinput is to be named W, the output is to be named Z, a Clock inputis to be used and an active low reset signal (Resetn) shouldasynchronously reset the machine. a) Draw the Mealy-type statediagram for the FSM. b) Write the VHDL code to implement theFSM.
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VHDL code for above required MEALY state diagramstandard logic library declarationlibrary IEEEuse IEEEstdlogic1164allentity
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