Write VHDL code (behavior model) to implement a 4-bit modulo-9counter and simulate your VHDL code of 4-bit modulo-9 counter inModelSim, and capture the screenshot
of your simulated waveform.
Assume clock period Tclk=100ns, initially, the counter is resetto Q3Q2Q1Q0=0000 youneed to simulate a complete counting cycle plus one more additionalclock period after it is reset to “0000” state.
